(1) Field of the Invention
The present invention relates to a transistor transistor logic (TTL) fundamental logic circuit and more particularly to a TTL logic circuit which is used in a large scale integrated circuit and whose signal amplitude is made small by adding a pnp transistor to an output npn transistor thereof.
(2) Description of the Prior Art
In general, known inverter circuits comprise a combination of an input npn transistor and an output npn transistor, and are used as a fundamental TTL gate circuit in a large scale integrated circuit (hereinafter referred to as an LSI). The signal amplitude, i.e., the potential difference between a high level logic signal and a low level logic signal of this inverter circuit, is very large as will be explained later, so that the propagation delay is large.
There is another known fundamental logic circuit comprising a clamp circuit which is connected in parallel to an output npn transistor and consists of a diode and a resistor connected in series. In this fundamental logic circuit, the signal amplitude can be very small and the propagation delay can be reduced. Such a prior art fundamental logic circuit is disclosed in, for example, U.S. Pat. No. 3,629,609.
However, since the clamp circuit is added to each fundamental logic circuit, the degree of integration of the LSI including such fundamental logic circuits is greatly reduced. Moreover, in such fundamental logic circuits, the potential level of the high level output signal becomes too low due to the insertion of the clamp circuit, and the noise immunity of the logic circuit deteriorates.